An area efficient 128 channel counter chip

An Area Eecient 128 Channel Counter Chip ?

A shift register of N bit length can be conngured (for most N) with a single exclusive-OR gate to generate periodically 2 N ? 1 diierent states. As each state is directly related to the number of clock pulses received, such a circuit can be used as a counter. The sequential readout of the bit pattern requires nearly no additional logic and many 'shift counters' can easily be daisy chained durin...

128 Bit Low Power and Area Efficient Carry Select Adder

Carry Select Adder (CSLA) which provides one of the fastest adding performance. Traditional CSLA require large area and more power. Recently a new CSLA adder has been proposed which performs fast addition, while maintaining low power consumption and less area. This work mainly focuses on implementing the 128 bit low power and area efficient carry select adder using 0.18 μm CMOS technology. Base...

An Area Efficient Wide Range On-Chip Delay Measurement Architecture

An efficient secure channel coding scheme based on polar codes

In this paper, we propose a new framework for joint encryption encoding scheme based on polar codes, namely efficient and secure joint secret key encryption channel coding scheme. The issue of using new coding structure, i.e. polar codes in Rao-Nam (RN) like schemes is addressed. Cryptanalysis methods show that the proposed scheme has an acceptable level of security with a relatively smaller ke...

Area and Power Efficient Router Design for Network on Chip

As network on chip (NoC) systems become more prevalent in today’s industry. Routers and interconnection networks are the main components of NoC. Therefore, there is a need to obtain low area and power models for these components so that we can better understand the area and power tradeoffs. In this paper a lowarea and power efficient NoC architecture is proposed by eliminating the virtual chann...